The RISC-V port was just merged to Linux a few minutes ago. This means we will be in the 4.15 release, which should be out about 10 weeks from last Sunday. As soon as the tarballs are created, the RISC-V Linux ABI will be stable, and
since we’ll ideally be in a glibc release that comes out soon after that we’ll be fully ABI stable by early in February.
RISC-V is a completely free and open ISA that hasn’t seen much adoption just yet.
It still needs (virtual) hardware specific support to actually run on anything if I’m not mistaken.
Out of tree driver do exist, again if memory serves me right.
See here for the source code:
https://github.com/riscv
Some of the reasons why we need something like RISC-V:
https://www.youtube.com/watch?v=zXwy65d_tu8
Edited 2017-11-16 22:19 UTC
Is RISC V used in the Talos workstations?
No, POWER9 chips.
Adopting new hardware depends on there being a useful OS for the hardware. Making linux for RISC-V means now there’s actually something to run on RISC-V hardware, so adoption should rise dramatically. Getting a repository for recompiled packages would also help increase adoption. When a RISC-V version of Ubuntu with all the associated packages is available, you’ll see RISC-V computers in the market.
ubuntu is not such a force on the desktop as to drive the adoption of a specific architecture.
RISC-V is going to be mainly used on the domain of academic research for a long time, if anything it may see some adoption on some mobile devices, or most likely IoT applications.
It’s too late for a non x86 part to make a dent on the desktop/laptop space.
Open source CPU will gain adoption in server/cloud platforms. Google and Rackspace already have open server using POWER9 CPU.
More info: “Introducing Zaius, Google and Rackspace^aEURTMs open server running IBM POWER9” (https://cloudplatform.googleblog.com/2016/10/introducing-Zaius-Googl…)
Zaius is an open design, but POWER9 is not open itself. RISC-V is open all the way down to the RTL
POWER9 is not open source. My bad.
This is not 100 percent sure. The ability for new cpu to enter market space are becoming more possible. Its all about the nm limit. We cannot keep on going smaller forever
3nm production is targeted to come on line for 2019. After that 1 nm and 0.5 nm might be possible. Then that is it. Then it will be focus on how the chip is internally designed and longer development cycles.
So it might not be possible for a non x86 at the moment but 5 to 10 years after silicon production hits limit all bets will be off particularly as production costs start to drop.
Risc-v chips form SiFive are already appearing in devices. You see the first chips in 2016 and the first IoT devices using Risc-v are already on the market.
What would it bring that ARM designs don’t? And so far the latter didn’t have much luck in breaking x86 monopoly on the desktop/laptop…
It looks like the Indian Institute of Technology is making a few versions of the RISC-V processor:
https://factordaily.com/india-chip-design-shakti-iit-madras/
That was my 1st though, BRICS countries insitutions are the first candidates to take this on seriously.
China have made their mind on mips some times ago but I bet they are looking into the arch right now.
What sort of performance are we talking about with RISC-V? Can this thing drive a graphics card and deliver VR capable 3d? Is it basically an academic toy? I understand the need and desire for a 100% open CPU platform, I want to know where we’re at and how useful this can be. There’s not exactly a lot of Moore’s law left to go. Architecture optimisation is going to become the new way to get performance.
Hi,
At this stage; I wouldn’t consider it an academic toy.
Understand that there are a lot of different design goals for CPUs. For some (e.g. desktop) you want very good performance on single-threaded branchy code and don’t care too much about design costs or extremely low power consumption. For others (e.g. GPU) you just want lots of floating point calculations in parallel, and don’t care much about single-thread branchy code or extremely low power consumption. For others (e.g. smartphones) you care a lot about extremely low power consumption.
I think RISC V will be used for cases where the main thing you care about is design costs (and not single-threaded performance or lots of floating point or power consumption). Mostly, I think it’ll be embedded deep inside things like chipsets and hard drives and TVs; where the main benefit is that you can “cut & paste” the CPU into a larger chip without paying licence fees to ARM.
– Brendan
The instruction set for RISC vs CISC only mattered when CPUs were MUCH faster than their data bus and relied on internal caches for the bulk of their speed. Modern buses can move data faster than the CPU can process it, and even if they didn’t modern caches are huge, so RISC needing 4X as many instructions (and that’s debatable) hasn’t mattered for years.
The speed of a processor is solely dependent on how good the internals are… branch prediction, out of order execution, scheduling to multiple execution units, out of order data fetch and store, etc. RISC-V is just a spec with a (relatively) simple example core meant for FPGAs. Until a major company dumps significant money into the guts, it’ll be slow.
There are 32 and 64 bit Risc-V chips already these are competitive with arm at the same nm. Talks the same kind of buses at the soc level.
The pro-type boards for the 64 bit Risc-V has pci-e support.
Performance is the same camp as Arm64 so not bad.
So the Risc-V design goes to a full proper 128bit processor. That is 128bit address space with 128bit registers and all forms of operations in those registers. We have not seen ASIC of 128 bit yet there are ASIC of 32 and 64 Risc-V.
In register count Risc-V matches SPARC, arm64 and mips cpus this is 1 under a powerpc chip in integer. Quite a few more integer registers than a x86 chip. This is 31 integer registers and 32 floating point.
Things will get interesting if we see ASIC 128bit Risc-V.
Performance is the same camp as Arm64 so not bad.
ARMv8 varies from single-issue micro controllers to wide Apple cores or server cores with hundreds GB/s of bandwidth.
Which ARM64 core are you referring to?
Risc-V Rocket core is competitive to Cortex-Mx microcontroller, but not to even slowest A53 core.
Edited 2017-11-18 22:25 UTC
Cortex-Mx are ARM64/64-bit? O_o
I didn’t said that. ARMv8-M for microcontrollers is 32-bit (Cortex-M22/33)
Oh well, I just got that impression from “Which ARM64 core are you referring to?” / as if it applied to all cores you mentioned a sentence earlier… NVM then.
https://hackaday.com/2017/10/04/sifive-announces-risc-v-soc/
64 bit version of a risc-v here per core performance matches to a A35 core yet it under half the size of a A35 core. Yes A35 is a arm64 core.
Yes per core A53-A73 are faster. Per area of silicon not so much because you can stuff a lot more risc-v cores in the same area. If you are talking consumed silicon area the current generations of Risc-v care competitive.
Just like arm cpu there are more than 1 risc-v design.
The Risc-v rocket is only a 32 bit version. So matching up against a Cortex-Mx that is also only 32 bit is doing quite well.
Reality here is the 64 bit Risc-v current produced is competitive with the entry level end of the arm64 directly and high end arm64 if you are working to processing power to area of silicon. Ok single threaded programs not going to be the best for the current risc-v.
Of course the optimisations that make A53+ of arm faster than the a35 per core are also not implemented in the current Risc-v in production. Those feature are for future generations of Risc-v chips.
Reality here is that high-end design cost hundreds of millions USD. At this point you have much more important things to worry about than the cost of arch license.
Not always true. Across a million units every cent counts.
Proven tools and wide industry support will save you much more.
~18 billions of ARM processors were sold in last year.
I don’t disagree. Risc-v is young. So it will take a while for it to get full set of tools under it feet.
Thing so remember here is that SIMD is from the 1960s. So by the 1980 early 1990s the core patents had died. Vector in a cpu core patents expire year 2005. Risc-v starts in 2010.
So arm instruction set problem is that it legacy. Even the new arm64 instruction set is still designed to avoid patents that no longer have to be avoided. Usage of vector in cpu core would even allow CISC instruction sets to be way more compact.
The issue here is implement vector in the cpu core properly is fairly much assured with x86, power and arm instruction sets it will require breaking the instruction sets. Risc-v being a fairly new design has the option of doing vector without the legacy overhead.
So it going to be interesting to watch Risc-v mature.
https://riscv.org/faq/
8.
We plan to define more optional instruction set extensions for RISC-V beyond the ones we already have, including Packed-SIMD Instructions (P), Bit Manipulation (B), Decimal Floating-Point (L), and Transactional Memory (T).
Edited 2017-11-21 08:44 UTC
Yes, however those are harder to measure (and put in spreadsheet or presentation) than licensing costs …so I can easily see management going for lack of licensing costs with RISC-V even when engineering team would prefer to stay on ARM.