Intel has set a concrete deadline for when it’ll finally have processors built on a 10nm process in the mainstream market: holiday season 2019.
While the company’s 14nm manufacturing process is working well, with multiple revisions to improve performance or reduce power consumption, Intel has struggled to develop an effective 10nm process. Originally mass production was planned for as far back as 2015. In April, the company revised that to some time in 2019. The latest announcement is the most specific yet: PC systems with 10nm processors will be in the holiday season, with Xeon parts for servers following soon after. This puts mainstream, mass production still a year away.
A seemingly endless string of delays. Things are not looking good for Intel.
This probably means AMD has it made all the way through 2020… if you check Intel’s roadmaps they don’t seem to be releasing any revolutionary architectural updates until after then if at all… there is a very good chance Intel will be at an IPC and clock deficit vs AMD at least for the entirety of 2019 Q2. By the time Intel has it’s next gen architecture rolling Zen 3 will be hitting….
This makes me wonder all the more what Jim Keller is up to…
While the existence of AMD PSP means that my next system will probably be Intel+me_cleaner, this is still very good news.
Intel needs strong competition.
And AMD is already at 7nm^aEUR|
Despite naming differences, intel’s 10nm is similar to other fabs’ 7nm.
Yeah, naming scheme in processors have always been a bit misleading
Especially from the AMD side.
Nah. Remember that AMD used SOI which isn’t directly comparable to bulk silicon, anything after 2009 is Globalfoundries and not AMD.
Some figures for comparison here: https://en.wikichip.org/wiki/45_nm_lithography_process
…and with 7nm shipping earlier than Intel’s 10nm, this means Intel lost their process advantage and even risk falling behind.
This is an indication of the fabless designer + fabs-for-hire model becoming the dominant mode of chip-making… soon “fabless” will be the norm for chip designers because it is the best way for fabs to achieve economies of scale … GlobalFoundries was a very clever move from AMD’s side.
Edited 2018-07-29 13:39 UTC
… and TSMc, Samsung et al are already starting to sample 5nm.
At this rate, Intel could find themselves 2 nodes behind and without any significant architectural advantage.
Fascinating times ahead.
Don’t think Intel is resting on its laurels.
Well actually they (effectively) have. 14 nm have improved but it’s still based on the same general parameters.
Until the next announcement that they worked for the last 5 years on a new groundbreaking architecture. Nothing is worrying me much on this side, and Intel still have quite a market and benchmark leadership, so…
And do you know what that attitude is called?
Resting on one’s laurels.
Have I said that Intel isn’t working at the next generation of processors ? Nope.
Have I said that Intel still have quite a leadership that offers them a delay ? Yes.
In both cases, this isn’t exactly resting on its laurels.
I was calling the precise thing that you actually said as the attitude of resting on one’s laurels. I wasn’t talking about Intel. I wasn’t talking about their market position.
I was talking about the exact words that I quoted. Whatever Intel may or may not be working on, and whether or not they may be in a good market position also, the attitude displayed in the thing I quoted IS one of resting on one’s laurels.
If they do have something behind the scenes, then they were obviously progressing a lot slower than as a company that is consistently inventing new things should be.
Resting on one’s laurels doesn’t have to be doing absolutely nothing, you just have to be progressing slower than expected of someone in that position.
Beginning to look like Intel will have nothing but market interia to compete with in the next few years
Regarding the number of x86 licensee, not much of a surprise there.
Hi,
I think it’s more likely that TSMc, Samsung, etc are going to find themselves 2 nodes ahead without any significant advantage (e.g. higher costs and lower yields for a “diminishing returns that diminished into insignificance” power consumption difference).
– Brendan
Yeah, keep telling yourself that.
Hi,
I really think you should do some reading: http://semimd.com/blog/tag/cobalt/
Basically; for the short term Intel is going to beat everyone else (because they’re using a mature process while everyone else is dealing with the “high cost, low yield” caused by an immature process); and for the medium term Intel is going to beat everyone else because they switched to materials (cobalt) that give better characteristics at the same size; and for the long term Intel are going to beat everyone else because they got a head start on materials (cobalt) that are needed to achieve even smaller sizes.
– Brendan
I’m sorry, but did you read the article you linked?
Intel does not have a leg up w. cobalt, they’re basically using it in the same capacity as everybody else, only that their process is 1 node behind.
I think a lot of people are still caught up in the dissonance (being a node behind now is “magically” a good thing) dealing with the shock that intel is, for the first time in a long while, behind in fab technology.
Edited 2018-08-01 19:56 UTC
Despite Intel’s marketing efforts, “similar” is still not the same.
Intel is literally a node behind. No bueno.
While THOM is CURED.
Its going to be Nintendo Days For Him.
https://www.youtube.com/watch?v=25Y_z_mt4X8
Freedom of speech is a wonderful thing.
One shouldn’t abuse it.
This ain’t kindergarten.
Just wondering, does Intel use ASML’s tech for its fabs?
Yes, and Intel is a major shareholder of ASML.
Some say that the main reason for delays are not really because Intel is unable to make 10nm chips, but because they are waiting for the ramp-up of EUV technology… provided by ASML.
This is a little aside matter, but that is small, on a scale that is hard to imagine in a mass-production context. I’ll assume, for this comment, that that’s the width of a silicon trace, developed during the doping process.
The covalent radius of silicon is 111pm, or 0.111nm. The crystal structure of silicon is face-centered cubic, so the side length of one silicon crystal structure is 543pm. That structure traverses 5 silicon atoms from vertex to vertex. (But, to avoid a fence-post error: vertices are joined, so traversing consecutive crystals means 4 atoms between vertices.)
The cube side of silicon is 0.543nm. Each crystal structure includes 6 shared atoms, bound or unbound, with adjacent crystals. So every crystal structure can claim 12 atoms for itself.
10nm=>18 crystal structures=>216 silicon atoms to traverse the shortest crystal axis. But even if the X axis is long enough, the Y and Z axes aren’t. The cube of 216 silicon atoms is 10,077,696 atoms, the smallest trace in a 10nm process.
A 7nm process gets shrunk likewise: 7nm=>13 crystal structures=>152 silicon atoms. The cube of 152 silicon atoms is 3,456,650 atoms. Is that currently the tiniest trace of conductive silicon?
My cell phone isn’t a smart phone, but it’s quite frankly the smartest non-smartphone I’ve ever seen. I’m not surprised that tech has gotten this far.
The scary part of all this? I think I could’ve calculated all of this in a Bash script. I actually cheated, sort of. I opened a LibreOffice spreadsheet for the quick’n’dirty work.
Maybe I got some bit of physics or three-dimensional math wrong. If someone can correct my calculations, it won’t detract from my wonder at the current state of technology. Today’s age of tech is like nothing ever seen before on planet Earth.
Nice math, and it demonstrates what dense chips have to deal with, but as WikiChip states, “The term “10 nm” is simply a commercial name for a generation of a certain size and its technology, as opposed to gate length or half pitch.”
In fact, everything from 22nm down is not actually indicative of the gate size, but merely marketing terms for a slight increase in gate density. If you look at the pitches for the processes, they’re still in the range of 30nm to 50nm. Gate shrinkage stalled after the 28nm process, but they still needed some way to distinguish one generation from the next, so they simply kept bumping down the size reference despite no longer matching it.