Intel Archive
Hot on the heels of AMD, here’s Intel’s next-generation processor, this time for the laptop market. Overall, Lunar Lake represents their second generation of disaggregated SoC architecture for the mobile market, replacing the Meteor Lake architecture in the lower-end space. At this time, Intel has disclosed that it uses a 4P+4E (8 core) design, with hyper-threading/SMT disabled, so the total thread count supported by the processor is simply the number of CPU cores, e.g., 4P+4E/8T. Gavin Bonshor at AnandTech The most significant change in Lunar Lake, however, has nothing to do with IPC improvements, core counts, or power usage. No, the massive sea change here is that Lunar Lake will do away with separate memory sticks, instead opting for on-die memory at a maximum of 32GB LPDDR5X. This is very similar to how Apple packages its memory on the M dies, and yes, this also means that as far as thin Intel laptops go, you’ll no longer be able to upgrade your memory after purchase. You choose your desired amount of memory at purchase, and that’s what you’ll be stuck with. Buyer beware, I suppose. We can only hope Intel isn’t going to default to 8GB.
Last week I wrote about Intel aiming to remove Xeon Phi support in GCC 15 with the products being end-of-life and deprecated in GCC 14. While some openly wondered whether the open-source community would allow it given the Xeon Phi accelerators were available to buy just a few years ago and at some very low prices going back years so some potentially finding use still out of them especially during this AI boom (and still readily available to buy used for around ~$50 USD), today the Intel Xeon Phi support was indeed removed. Michael Larabel Xeon Phi PCIe cards are incredibly cheap on eBay, and every now and then my mouse hovers over the buy button – but I always realise just in time that the cards have become quite difficult to use, since support for them, already sparse to begin with, is only getting worse by the day. Support for them was already removed in Linux 5.10, and now GCC is pulling he plug too, so the only option is to keep using old kernels, or pass the card on to a VM running an older Linux kernel version, which is a lot of headache for what is essentially a weird toy for nerds at this point. GCC 15 will also, sadly, remove support for Itanium, which, as I’ve said before, is a huge disgrace and a grave mistake. Itanium is the future, and will stomp all over crappy architectures like x86 and ARM. With this deprecation, GCC relegates itself to the dustbin of history.
Intel and AMD both tried to ship iGPUs fast enough to compete with low end discrete cards over the past 10 years with mixed results. Recently though, powerful iGPUs have been thrown back into the spotlight. Handhelds like Valve’s Steam Deck and ASUS’s ROG Ally demonstrated that consumers are willing to accept compromises to play games on the go. AMD has dominated that market so far. Valve’s Steam Deck uses AMD’s Van Gogh APU, and the ROG Ally uses the newer Phoenix APU. Unlike Van Gogh, Phoenix is a general purpose mobile chip with both a powerful CPU and GPU. Phoenix doesn’t stop at targeting the handheld segment, and threatens Intel’s laptop market share too. In response, Meteor Lake brings a powerful iGPU to the party. It has the equivalent of 128 EUs and clocks up to 2.25 GHz, making it modestly wider and much faster than Raptor Lake’s 96 EU, 1.5 GHz iGPU. Raptor Lake’s Xe-LP graphics architecture gets replaced by Xe-LPG, a close relative of the Xe-HPG architecture used in Intel’s A770 discrete GPU. At the system level, Meteor Lake moves to a GPU integration scheme that better suits a chiplet configuration where the iGPU gets significant transistor and area budget. I’ll be testing Meteor Lake’s iGPU with the Core Ultra 7 155H, as implemented in the ASUS Zenbook 14. I purchased the device myself in late February. Chips and Cheese I’m absolutely here for the resurgence in capable integrated GPUs, both for PC gaming on the go and for better graphics performance even in thinner, smaller laptops. I would love to have just a bit more graphics power on my thin and small laptop so I can do some basic gaming with it.
Since the mid-90’s with the P6 micro-architecture for the Pentium Pro as the sixth-generation x86 microarchitecture, Intel has relied on the “Family 6” CPU ID. From there Intel has just revved the Model number within Family 6 for each new microarchitecture/core. For example, Meteor Lake is Family 6 Model 170 and Emerald Rapids is Family 6 Model 207. This CPU ID identification is used within the Linux kernel and other operating systems for identifying CPU generations for correct handling, etc. But Intel Linux engineers today disclosed that Family 6 is coming to an end “soon-ish”. Michael Larabel They should revive the ix86 family name, and call the next generation i786. It sounds so much cooler, even if these names have become rather irrelevant.
Nearly one year ago Intel published the X86S specification (formerly stylized as “X86-S”) for simplifying the Intel architecture by removing support for 16-bit and 32-bit operating systems. X86S is a big step forward with dropping legacy mode, 5-level paging improvements, and other modernization improvements for x86_64. With the Linux 6.9 kernel more x86S bits are in place for this ongoing effort. Michael Larabel I doubt we’ll see much fallout from these changes.
US chip company Intel will make high-end semiconductors for Microsoft, the companies announced, as it seeks to compete with TSMC and Samsung to supply the next generation of silicon used in artificial intelligence for customers around the world. Chief executive Pat Gelsinger said at a company event on Wednesday that Intel is set to “rebuild Western manufacturing at scale,” buoyed by geopolitical concerns in Washington about the need to bring leading-edge manufacturing back to the US. Michael Acton Having our entire advanced chip industry built atop one Dutch company and one company on an island China would love to invade is not exactly the recipe for a stable supply chain. I think it’s a great idea to build capacity in the US and Europe, and if Intel’s the one to do it – with lavish government funding, I might add – then so be it. We’d all love for it to be more diverse than that, but the sad reality is that building advanced chip factories is really hard and really expensive, and very few companies have both the knowledge and money to do so.
Around 1977, Intel released a floppy disc controller (FDC) chip called the 8271. This controller isn’t particularly well known. It was mainly used in business computers and storage solutions, but its one breakthrough into the consumer space was with the BBC Micro, a UK-centric computer released in 1981. There are very few easily discovered details about this chip online, aside from the useful datasheet. This, combined with increasing observations of strange behavior, make the chip a bit of an enigma. My interest in the chip was piqued when I accidentally triggered a wild test mode that managed to corrupt one of my floppy discs even though the write protect tab was present! You can read about that here. Can we reverse engineer a detailed understanding of how it works? What wonders will we find? Chris Evans This thing is wild.
After three years of delays, Merced shipped as Itanium on the 29th of May in 2001. The first OEM systems from HP, IBM, and Dell were shipped in June. Itanium, whose architecture was now referred to as IA-64, was a 6-wide VLIW chip running at either 733 to 800 MHz with a 266 MT/s front side bus. It had 16K of L1 cache, 96K of L2 cache, 2 or 4 MB of L3 cache, and it was a single core chip on socket PAC418 built on a 180nm process. That this chip under performed is an understatement. Given the long development time, multi-billion-dollar development cost, significant hype, and claims that it would out-compete everything on the market… Itanium was a massive failure. The 32 bit x86 chips of the time were able to best it in most workloads. Embarrassingly, the Pentium 4 (whose own performance wasn’t that good) beat Itanium on integer performance and memory bandwidth. Those areas where the chip was strong were in transaction processing and scientific applications. John Crawford, Merced project leader at Intel, reflects: “Everything was crazy. We were taking risks everywhere. Everything was new. When you do that, you’re going to stumble.” The five hundred person team working on the chip was also relatively inexperienced, and disagreements between HP and Intel led to many compromises in design. Bradford Morgan White Itanium is the future. This entire article is anti-Itanium propaganda and misinformation. Do your own research.
Intel’s Optane memory modules launched with a lot of fanfare in 2015, and were recently discontinued, in 2022, with similar fanfare. It was a sad day for me, a lover of abstraction-breaking technologies, but it was forseeable and understandable. At the time of Optane’s launch, a lot of us were excited about the idea of having a new storage tier, sitting between DRAM and flash. It was announced as having DRAM endurance and speed with the persistence and size of flash. It was a futuristic memory technology, but the technology of the future met the full force of Wright’s Law. Nima Badizadegan I definitely remember Optane being presented as a huge deal, but it seems it fell between the cracks of other technologies developing around it and their prices dropping fast.
Chip companies like Qualcomm, Nvidia, and AMD are all either planning or said to be planning another attempt at making Arm chips for the consumer PC market. Qualcomm is leading the charge in mid-2024 with its Snapdragon X Elite and a new CPU architecture called Oryon. And Reuters reported earlier this week that Nvidia and AMD are targeting a 2025 release window for their own Arm chips for Windows PCs. If these companies successfully get their chips into PCs, it would mostly come at Intel’s expense. But Intel CEO Pat Gelsinger doesn’t seem worried about it yet, as he said on the company’s most recent earnings call. The biggest issue for Windows on ARM will be, as always, application compatibility. ARM applications haven’t exactly been pouring in for Windows, and translation layers in Windows haven’t been earth-shattering either. As long as this problem remains, Intel indeed has little to worry about. I’m just excited there’s finally some movement in ARM laptops, because Linux is exceptionally well positioned for the transition to ARM. Every major distribution has a fully functional ARM version, with pretty much full package repository support. There really is very little difference in running desktop Linux on ARM (or even POWER9, for that matter). The power of open source.
The Intel 14th Gen Core series is somewhat of a somber swansong to the traditional and famed Core i series naming scheme, rounding off what feels like the end of an era. With the shift to their upcoming Meteor Lake SoC, the impending launch of the new naming scheme (Core and Core Ultra) branding, and what Intel hopes to be a groundbreaking mobile chiplet-based architecture. The crux of the analysis is if you’re upgrading from an older and outdated desktop platform, the Intel 14th Gen series is a solid performer, but there’s still value in current 13th Gen pricing. Those must be considered in the current global financial situation; some users may find a better deal. If you already have 12th or 13th Gen Core parts, then there’s absolutely no reason to upgrade or consider 14th Gen as a platform, as none of the features (mainly software) justify a sidegrade on which is ultimately the same platform and the same core architecture. AnandTech always delivers. Unlike Intel.
A circuit called the flip-flop is a fundamental building block for sequential logic. A flip-flop can hold one bit of state, a “0” or a “1”, changing its value when the clock changes. Flip-flops are a key part of processors, with multiple roles. Several flip-flops can be combined to form a register, holding a value. Flip-flops are also used to build “state machines”, circuits that move from step to step in a controlled sequence. A flip-flops can also delay a signal, holding it from from one clock cycle to the next. Intel introduced the groundbreaking 8086 microprocessor in 1978, starting the x86 architecture that is widely used today. In this blog post, I take a close look at the flip-flops in the 8086: what they do and how they are implemented. In particular, I will focus on the dynamic flip-flop, which holds its value using capacitance, much like DRAM. Many of these flip-flops use a somewhat unusual “enable” input, which allows the flip-flop to hold its value for multiple clock cycles. More in-depth chip content. This type of content has been coming up a lot lately.
Intel is a newcomer to the world of discrete graphics cards, and the company’s Xe architecture is driving its effort to establish itself alongside AMD and Nvidia. We’ve seen Xe variants serve in integrated GPUs and midrange discrete cards, but Intel’s not stopping there. Their GPU ambitions extend to the datacenter and supercomputing markets. That’s where Ponte Vecchio (PVC) comes in. Like other compute-oriented GPUs, PVC goes wide and slow. High memory bandwidth and FP64 throughput differentiate it from client architectures, which emphasize FP32 throughput and use caching to reduce memory bandwidth demands. Compared to Nvidia’s H100 and AMD’s MI210, PVC stands out because it lacks fixed function graphics hardware. H100 and MI210 still have some form of texture units, but PVC doesn’t have any at all. Combine that with its lack of display outputs, and calling PVC a GPU is pretty funny. It’s really a giant, parallel processor that happens to be programmed in the same way you’d program a GPU for compute. Another great feature from Chips and Cheese. Speaking of Intel – the company also unveiled that Meteor Lake CPUs are coming to the desktop in 2024.
The European Commission has fined Intel $400 million (EUR376 million) for hindering competitors’ access to the market through naked restrictions between 2002 and 2007. The fine comes after a long-running antitrust court battle dating back to 2009 when the Commission initially fined Intel a record $1.13 billion for abuse of dominance. While some of Intel’s actions, like hidden rebates, were dropped on appeal due to lack of evidence of harm, the Commission upheld that Intel paid PC manufacturers to delay or limit products using AMD processors. Specifically, the Commission cited examples where Intel paid HP not to sell AMD-powered business PCs to small and medium businesses through direct channels from 2002-2005. It also paid Acer to delay the launch of an AMD-based notebook from late 2003 to early 2004. Intel also paid Lenovo to push back the launch of AMD notebooks by six months. While it’s great that fines are being levied for these crimes, the problem is that the damage is already done and a fine won’t actually undo said damage. Of course, there’s no way to know exactly what the industry would’ve looked like had Intel not committed these crimes, but I feel like quite often these fines are more seen as a cost of doing business than as an actual detrimental punishment. It reminds me a lot of speeding tickets – they can be devastating to somebody of lower means, but to the upper classes they’re just the cost of driving a car and barely even register. I’d be much more in favour for not just fining companies that violate antitrust, but also going after the people within those companies that enabled and advocated for such behaviour through massive personal fines and jail time. None of the people involved will feel even the slightest bit of sting from their actions, and will do it all over again next time they get the chance.
Today we have something that has taken months to write, and we feel that the best we have done is to give a sense of what Intel’s coolest CPU is capable of. The Intel Xeon MAX 9480 combines 56 cores with memory on the package. The memory is not standard DDR5. Instead, it is 64GB of HBM2e, the same kind of memory found on many GPUs and AI accelerators today. What seemed like a straightforward review at the outset became absolutely fascinating, especially when we pulled all of the DDR5 memory from a system and watched it boot. Let us get to it. Few of us will ever get to use one of these – especially since they’re specifically designed for a supercomputer – but maybe we’ll get lucky and they end up on eBay or AliExpress ten years from now.
During the opening keynote at Intel’s Innovation event in San Jose, Chief Executive Officer Pat Gelsinger unveiled a score of details about the upcoming Meteor Lake client platform. Intel’s Meteor Lake marks the beginning of a new era for the chipmaker, as they move away from the chaotic Intel 7 node and go into a rollout of their Foveros 3D packaging with EUV lithography for their upcoming client mobile platform. Meteor Lake uses a tiled, disaggregated chiplet architecture for its client-centric processors for the first time, changing the very nature of Intel’s consumer chips going forward. And, according to Intel, all of these changes have allowed them to bring some significant advancements to the mobile market. Intel’s first chiplet-based consumer CPU breaks up the common functions of a modern CPU into four individual tiles: compute, graphics, SoC, and an I/O tile. Within the makeup of the compute tile is a new pair of cores, a P-core named Redwood Cove and a new E-core called Crestmont. Both these cores promise IPC gains over their previous counterparts, but perhaps the most interesting inclusion is a new type of E-core embedded directly into the SoC tile, which Intel calls ‘Low Power Island.’ These new LP E-cores are designed with the idea that light workloads and processes can be taken off the more power-hungry compute tile and offloaded onto a more efficient and lower-powered tile altogether. Other major additions include a first-for-Intel Neural Processing Unit (NPU), which sits within the SoC tile and is designed to bring on-chip AI capabilities for workloads and inferencing, paving the way for the future. With Meteor Lake, Intel is aiming to put themselves in a more competitive position within the mobile market, with notable improvements to compute core hierarchy, Intel’s Xe-LPG Arc-based graphics tile looking to bolster integrated graphics capabilities, and an NPU that adds various AI advantages. Meteor Lake also sets the scene for Intel and modular disaggregation, with Foveros 3D packaging set to become a mainstay of Intel’s processor roadmap for the future, with the Intel 4 process making its debut and acting as a stepping stone to what will become Intel’s next mainstay node throughout its fabs, Intel 3. AnandTech takes its usual in-depth look at Intel’s upcoming Meteor Lake platform, which seems like it will be a rather radical shift for the company. It’s also the first generation whithout Intel’s Core ix naming scheme, so things might be a bit confusing for a while post-launch.
Thunderbolt 5 will deliver 80 gigabits per second (Gbps) of bi-directional bandwidth, and with Bandwidth Boost it will provide up to 120 Gbps for the best display experience. These improvements will provide up to three times more bandwidth than the best existing connectivity solution, providing outstanding display and data connections. Thunderbolt 5 will meet the high bandwidth needs of content creators and gamers. Built on industry standards – including USB4 V2 – Thunderbolt 5 will be broadly compatible with previous versions of Thunderbolt and USB. That’s some serious speed for a cable.
SoftBank has been gearing up anchor investments in Arm Holdings among its clients and partners for months now (ahead of the upcoming IPO) and apparently Intel is among them. In a call for the Goldman Sachs Communacopia & Technology Conference, the head of the company’s foundry business unit confirmed that the chip giant has made an investment in Arm because its technology is strategically important for both Intel Foundry Services and Altera FPGA unit. This doesn’t seem to be an indicator Intel is interested in making ARM chips – it seems to have more to do with Intel becoming a fab for other companies’ ARM chips.
Intel has announced two new x86-64 instruction sets designed to bolster and offer more performance in AVX-based workloads with their hybrid architecture of performance (P) and efficiency (E) cores. The first of Intel’s announcements is their latest Intel Advanced Performance Extensions, or Intel APX as it’s known. It is designed to bring generational, instruction set-driven improvements to load, store and compare instructions without impacting power consumption or the overall silicon die area of the CPU cores. Intel has also published a technical paper detailing their new AVX10, enabling both Intel’s performance (P) and efficiency (E) cores to support the converged AVX10/256-bit instruction set going forward. This means that Intel’s future generation of hybrid desktop, server, and workstation chips will be able to support multiple AVX vectors, including 128, 256, and 512-bit vector sizes throughout the entirety of the cores holistically. The basic gist is that these two new instruction sets should bring more performance at lower energy usage.
Some huge news today. Intel has started to notify its ecosystem saying that it will stop direct investment in the Next Unit of Compute (NUC) business. For the handful of STH readers who are unaware, Intel not only makes chips but they also make systems. Earlier this year, we covered that Intel was exiting the server business and selling it to MiTAC. Now its line of PCs is being sunset as well. Luckily, the market for small, powerful computers is more alive than it’s ever been, and there are countless OEMs making both AMD and Intel tiny computers these days. My only concern would be that Intel exiting this market might mean the kinds of parts needed for tiny computers like the NUC also become harder to source, but since you can always use laptop parts, I doubt that’s going to be an issue.
